QUALITY
OUR QUALITY PHILOSOPHY
WHAT WE HAVE ACHIEVED
Our reliability qualification for discrete devices is conducted mainly with reference to AEC-Q101. The updated AEC-Q101E-2021 specification defines 37 general qualification tests, but not all are mandatory. The required tests must be selected according to factors such as device category, package type, and mounting configuration.
The qualification framework specifies the minimum stress-test requirements and reference conditions for discrete semiconductor components. Its objective is to verify that a device can successfully pass the required stress tests in real-world applications and be recognized as meeting defined levels of quality and reliability. Under AEC-Q101, Group A and Group B tests are defined according to the following criteria and conditions:
| No. | Test Item | Abbrev. | notes | Samples | Lots | Acceptance | Standard | Main Test Conditions |
|---|---|---|---|---|---|---|---|---|
| A1 | Pre-Conditioning | PC | GS | 77 | 3 | 0 Fails | J-STD-020
JESD22A113 |
Performed before A2, A3, A4, A5 and C8 for all SMD devices; electrical test before and after PC |
| A2 | Biased Highly Accelerated Stress Test | BHAST | DGUV3 | 77 | 3 | 0 Fails | JESD22A-110 | 1) 96 h at 130℃ / 85%RH;
2) Vbe = 80% Vbemax (stop if arcing occurs, typically >42 V); 3) Electrical test before/after |
| A2alt | High Temperature High Humidity Reverse Bias | H³TRB | DGUV3 | 77 | 3 | 0 Fails | JESD22A-101 | 1) 1000 h;
2) 85℃ / 85%RH; 3) Vbe = 80% Vbemax (up to 100 V or device limit); 4) Electrical test before/after |
| A3 | Unbiased HAST | UHAST | DGU | 77 | 3 | 0 Fails | JESD22A-118
JESD224-101 |
1) 96 h;
2) 130℃ / 85%RH; 3) Electrical test before/after |
| A3alt | Autoclave Test (Pressure Cooker) | AC | 77 | 3 | 0 Fails | JESD224-102 | 1) 96 h;
2) 121℃ / 100%RH / 101 kPa; 3) Electrical test before/after |
|
| A4 | Temperature Cycling | TC | DGUV3 | 77 | 3 | 0 Fails | JESD224-104
Appendix6 |
1) 1000 cycles;
2) -55℃ ↔ max rated Tj (≤150℃); If TA(max)=Timax+25℃ or 175℃, cycles may reduce to 400 |
| A4a | Temperature Cycling Delamination Test | TCHT | DGUV1，2 | 77 | 3 | 0 Fails | JESD224-104
Appendix6 |
125°C; de-lid 5 units for wire bond pull; for wire diameter ≤5 mil; may use subset of A4 samples |
| A4alt | Temperature Cycling Delamination Test | TCDT | DGUV1，2 | 77 | 3 | 0 Fails | JESD22A-104
Appendix6 J-STD-035 |
1) Perform C-SAM after TC;
2) If delamination detected, de-lid worst 5 pcs for wire pull; 3) If no delamination, de-lidding not required |
| A5 | Intermittent Operating Life | IOL | DGPTUW3 | 77 | 3 | 0 Fails | MIL-STD-750
Method 1037 |
1) Cycles per Table 2A;
2) Ta=25℃; 3) Ensure ΔTj ≥ 100℃ (do not exceed abs max); 4) Electrical test before/after |
| A5alt | Power Temperature Cycling | PTC | DGTUW | 77 | 3 | 0 Fails | JESD22A-105 | Used if IOL cannot achieve Tj ≥ 100℃;
1) Cycles per Table 2A; 2) −40℃ to 105℃, 20 min transitions; 3) ton/toff = 5 min; 4) Electrical test before/after |
| No. | Test Item | Abbrev. | notes | Samples | Lots | Acceptance | Standard | Main Test Conditions |
|---|---|---|---|---|---|---|---|---|
| B1 | High-Temperature Reverse Bias | HTRB | DGKPVX 3 | 77 | 3 | 0 Fails | MIL-STD-750 |
1. 1000 h; 2. Vbe=Vbemax; 3. Ta=150℃ (adjust per leakage); 4. Electrical test before/after; 5. Remove bias only at Ta=30℃/−5℃; 6. For bipolar/Schottky: de-lid 5 pcs for wire pull after test |
| B2 | High-Temperature Gate Bias | HTGB | DGMPU3 | 77 | 3 | 0 Fails | JESD22A-108 | 1. Test duration: 1000 hours
2. Tj reaches rated maximum / 150 °C 3. VGS = maximum rated positive gate voltage; drain–source shorted 4. If junction temperature increases by 25 °C, the test duration shall be reduced to 500 hours 5. Electrical testing shall be performed before and after the test |
| B2 | High-Temperature Gate Bias | HTGB | DGMPU3 | 77 | 3 | 0 Fails | JESD22A-108 | 1. Test duration: 1000 hours
2. Tj reaches rated maximum / 150 °C 3. VGS = maximum rated positive gate voltage; drain–source shorted 4. If junction temperature increases by 25 °C, the test duration shall be reduced to 500 hours 5. Electrical testing shall be performed before and after the test |
Customized Reliability Qualification Solutions
Based on the AEC-Q101 standard, Thinkantech performs comprehensive reliability certification for its discrete devices. To meet specific application requirements or customer needs, XIN GAN XIAN also supports customized reliability and quality qualification programs, offering additional test items beyond the standard AEC-Q101 framework.
| Category | No. | Conditions | Abbrev. | Qty | Duration | Standard | Notes | ||
|---|---|---|---|---|---|---|---|---|---|
| Moisture Sensitivity Level | 1 | MSL3 |
BARC：125℃24HRS； SOAK： 60℃60MH, 40HRS REFLOW：260℃，3 times |
80 pcs × 4 | / | J-STD-020 | Electrical parameters before and after testing shall meet the specifications.
Parameter variation before and after testing shall remain within ±20% of the initial value. IGSS / IDSS shall remain within 10× of the initial value. |
Testing must be completed within 48 hrs | • Applicable to SMD devices only |
| High-Temperature High-Voltage Bias Stress | 2 | H3TR8 | Ta=85℃/85%RH
High Temperature Humidity Reverse Bias H3TRB VDS=80V， G-S shorted |
80 pcs | 1000h | JES022A-101 | Testing must be completed within 48 hrs | Electrical test at 0 / 500 / 1000 cycles | |
| Unbiased Highly Accelerated Stress Test | 3 | UHAST | Ta=130℃ 85%MH | 80 pcs | 96h | JES022A-118
JESD224-101 |
Testing must be completed within 48 hrs | Electrical test at 0 / 48h / 96h cycles | |
| Temperature Cycling | 4 | TC | Temperature range: –55 °C to +150 °C
Temperature Cycling (TC): Transition time: 11 minutes Dwell time: 20 minutes |
80 pcs | 1000cyc | JES022A-104
Appendix6 |
Electrical parameters before and after testing shall meet the specifications.
Parameter variation before and after testing shall remain within ±20% of the initial value. IGSS / IDSS shall remain within 5× of the initial value. |
Complete within 2–48 hrs | Electrical test at 0 / 500 / 1000 cycles |
| Intermittent Operating Life (IOL) | 5 | IOL |
Ta=75℃，Tvjmax=150℃, ΔTj=100℃; Vg=0V/6V |
80 pcs | 1000h | MIL-STD-750
Method 1037 |
Testing must be completed within 96 hrs | Electrical test at 0 / 500 / 1000 hours | |
| High-Temperature Reverse Bias | 6 | HTRB | Ta=150℃, VDS=860V, G-S shorted | 80 pcs | 1000h | JESD22A-108 | Testing must be completed within 24 hrs | Electrical test at 0 / 500 / 1000 hours | |
| High-Temperature Gate Bias | 7 | HTGB | Ta=150℃, VGS=6V, D-S shorted | 80 pcs | 1000h | JESD22A-108 | Testing must be completed within 96 hrs | Electrical test at 0 / 500 / 1000 hours |
QG324 defines a comprehensive reliability qualification process for automotive-grade power modules, enabling effective verification of product robustness. This process helps manufacturers gain deeper insight into the reliability performance of their modules, thereby accelerating product development and optimizing manufacturing processes.
Module characteristic tests are primarily used to validate the basic electrical functionality and mechanical properties of the power module.
In addition, these tests allow early detection and evaluation of potential weak points that may not immediately cause functional degradation or failure, including issues related to component layout, assembly quality, interconnection technology, and semiconductor integrity.
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Module Characterization Test Equipment Solutions
Environmental testing is primarily used to verify the suitability of power electronic modules for automotive applications. These tests include physical analysis, electrical and mechanical parameter verification, and insulation property evaluation.
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Environmental Test Equipment Solutions
Life tests are primarily used to verify whether the product meets the required operational and storage lifetime under specified conditions, to identify design weaknesses, and to determine failure mechanisms. For example, power cycling tests are mainly used to trigger and accelerate typical degradation processes in power electronic modules.
This process generally distinguishes between two types of failure mechanisms:
Chip-near fatigue failure, occurring close to the chip interconnections
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Lifetime Test Equipment Solutions
| No. | Test Item | Abbrev. | Standard | Main Test Conditions |
|---|---|---|---|---|
| QC-01 | Parasitic Inductance | Lp | Determines the parasitic stray inductance (Lp) of the module’s primary current path and main terminals. | |
| QC-02 | Thermal Resistance | Rh | IEC 60747-15:2012, section 5.3.2 (double pulse testing) | |
| QC-03 | Short-Circuit / Over-current Test | IEC 60747-15:2012, section 5.3.6 | ||
| QC-04 | Insulation Test | AC | JESD22A-118 | Insulation Resistance Test:
1. Pre-conditioning: 5 ± 2°C, 8 h 2. Condition: 23 ± 5°C, 90 (+10/–5)% RH, 86–106 kPa, 8 h 3. V ≥ 1.5 × Vbemax & V ≥ 50 W; insulation resistance ≥ 100 MΩ 4. Record data at ≥ 30-min intervals Dielectric Strength Test: 1. Pre-conditioning: 30 ± 2°C until fully stabilized 2. Condition: 23 ± 5°C, 93 (+10/–5)% RH, 86–106 kPa, 48 h 3. Post-test insulation resistance ≥ 100 MΩ |
| QC-05 | Mechanical Parameter Inspection | JESD224-102 |
| No. | Test Item | Abbrev. | Standard | Main Test Conditions |
|---|---|---|---|---|
| QE-01 | Temperature Shock | TST | IEC 60749-25:2003条件G | 1. Temperature: −40°C / +125°C
2. Transfer time ≤ 30 s 3. Dwell time ≥ 15 min 4. ≥ 1000 cycles |
| QE-03 | Mechanical Vibration | V | IEC 60068-2-6 | Simulates vibration loads during vehicle operation; verifies resistance to vibration-related failure modes (e.g., material fatigue, device detachment) |
| QE-04 | Mechanical Shock | MS | IEC 60068-2-27 | 1. Peak acceleration: 500 m/s²
2. Duration: 6 ms 3. 10 shocks per direction (±X, ±Y, ±Z) 4. DUT quantity: 6 units |
| No. | Test Item | Abbrev. | Standard | Main Test Conditions |
|---|---|---|---|---|
| QL-01 | Power Cycling (Short Cycle) | PCsec | IEC 60749-34:2011 | |
| QL-02 | Power Cycling (Long Cycle) | Pcmin | IEC 60749-34:2011 | |
| QL-03 | High-Temperature Storage | HTS | IEC 60749-6:2002 | 1.Temperature：≥125℃
2.Duration1000h |
| QL-04 | Low-Temperature Storage | LTS | JEDEC RESD-22 A119:2015 | 1.Temperature：≤-40℃
2.Duration1000h |
| QL-05 | High-Temperature Reverse Bias | HTRB | 1.Temperature:Tjmax
2.V≥80V max 3.Duration≥1000h |
|
| QL-06 | High-Temperature Gate Bias | HTGB | IEC 60747-9:2007 section 7.1.4.1 (IGBT) | 1.Temperature:Tjmax
2.VGE=VGE max 3.Duration≥1000h |
| QL-07 | High-Temperature High-Humidity Bias | HSTRB | IEC 60747-8:2010 (MOSFET) | 1.Temperature:Tjmax
2.VGS=VGS min 3.Duration≥1000h |
| QL-08 | High-Temperature High-Humidity Reverse Bias | HSTRB | IEC 60747-2:2016 (Diode) | 1.Temperature:85℃ Moisture: 85%RH
2.VR=80V max/80V 3.Duration≥1000h |
QUALIFICATION
THINKANTECH always adheres to the strategy of “Built on Technology, Driven by Research and Development,” THINKANTECH pursues technological breakthroughs while embedding high quality standards throughout its development. The continuous growth in patent numbers serves as strong evidence of this commitment.
Since its founding, the company has obtained over 120 patents and successfully achieved two authoritative quality system certifications:
1. ISO 9001 Quality Management System Certification, established by the International Organization for Standardization (ISO)
2. IATF 16949 International Quality System Certification, focused on industry-specific requirements
These achievements comprehensively demonstrate THINKANTECH’s robust capability in quality management.
- Certified to ISO9001 Production Quality Management System
- Certified to IATF16949 Automotive-Grade Component Production Quality Management System
PATENT CERTIFICATES
Cumulatively, 120+ patents have been filed, covering the full chain of GaN and SiC device design, packaging, and testing.
- a HTRB reliability testing method for power devices
- A preparation method for power semiconductor devices and the power semiconductor device
- A double-sided heat dissipation integrated GaN module
- A preparation method for power devices and the power device
- A double-groove power device and its preparation method
- A shielded-gate power device preparation method and the shielded-gate power device
- A super-junction MOSFET preparation method and super-junction MOSFET
- An IGBT power device preparation method and IGBT power device
- A SiC module power device structure and its manufacturing process
- A SiC module power device packaging structure
- An IGBT module structure
- A preparation method for power semiconductor devices and the power semiconductor device
- Packaging frame (TOLT)
- A SiC device with integrated structure and its preparation method
- A Lead frame
- A SiC MOS with inclined J-FET region and its preparation method
- A GaN power module and the power semiconductor device
- A SiC-MOS device, an inverter, and an electronic equipment
- A dual-gate semiconductor device with timing difference and its preparation method
- A GaN power module
- Clamping device for power device processing
- A RC-IGBT device preparation method and the RC-IGBT device
- A GaN power module
- A GaN device power module
- A separated gate-groove MOSFET device
- A power device with integrated drive circuit
- A chip structure, a power device, and an electronic equipment
- A MOSFET device preparation method and the MOSFET device
- A GaN power module
- An integrated GaN IGBT device preparation method and the IGBT device
- A MOSFET device with integrated heterojunction diode and its preparation method
- A MOSFET device with integrated JFET preparation method and the MOSFET device
- A junction terminal structure and its preparation method with the semiconductor device
- A novel reverse-conduction GaN power device
- A packaging structure and a method for wide-bandgap semiconductor power modules
- A GaN device for efficient heat dissipation and reverse conduction
- A GaN power device with controllable field plate
- A flip-chip GaN power device with improved heat dissipation
- A GaN power device
- A GaN power device with integrated freewheeling diode and its packaging method
- A GaN device with improved heat dissipation and its integrated module with driver components
- A SiC power device combining MOSFET and IGBT structures
- A trench-gate field-effect transistor
- A symmetric-gate GaN device and its parallel structure
- A GaN half-bridge power module
- A GaN device with low inter-gate impedance and its parallel structure
- A GaN power device with improved heat dissipation
- A monolithic integrated GaN chip
